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92706 / 81205hkim b8-7735 no.7972-1/25 ver.1.00 lc875bp4a lc875bm2a lc875bj0a LC875BH4A overview the lc875bp4a, lc875bm2a, lc875bj0a, LC875BH4A is 8-bit single chip microcontroller with the following one- chip features : ? cpu : operable at a minimu m bus cycle time of 100ns ? on-chip rom capacity : lc875bp4a 256k bytes : lc875bm2a 224k bytes : lc875bj0a 192k bytes : LC875BH4A 176k bytes ? on-chip ram capacity : 4k bytes ? two high performance 16-bit timer/counters (can be divided into 8-bit timers) ? four 8-bit timers with prescalers ? timer for use as date/time clock ? two synchronous serial i/o ports (with automatic block transmit/receive function) ? one asynchronous/synchronous serial i/o port ? two uart ports (full duplex) ? 12-bit pwm 4 ? 12-channel 8-bit ad converter ? high speed clock counter ? system clock divider ? 27-source 10-vectored interrupt system ordering number : enn7972 cmos ic rom 256k/224k/192k/176k byte, ram 4096k byte on-chip 8-bit 1-chip microcontroller any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before using any sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein.
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-2/25 features ? read only memory (rom) ? 262144 8-bits (lc875bp4a) ? 229376 8-bits (lc875bm2a) ? 196608 8-bits (lc875bj0a) ? 180224 8-bits (LC875BH4A) ? random access memory (ram) : 4096 9-bit ? bus cycle time ? 100ns (10mhz) note : bus cycle time indicates the speed to read rom. ? minimum instruction cycle time (tcyc) ? 300ns (10mhz) ? ports ? input/output ports input/output programmable for each bit individually 64 (p1n, p2n, p3n, p70 to p73, p8n, pan, pbn, pcn, s2pn, pwm0, pwm1, xt2) data direction programmable in two bits 16 (pen, pfn) data direction programmable in nibble units 8 (p0n) ? input ports 1 (xt1) ? oscillator pins 2 (cf1, cf2) ? reset pin 1 (res ) ? power supply 8 (v ss 1 to 4, v dd 1 to 4) ? timer ? timer 0 : 16-bit timer/counter with capture register mode 0 : 8-bit timer with 8-bit programmable presca ler (with an 8-bit capture register) 2-channels mode 1 : 8-bit timer with an 8-bit programmable prescal er (with an 8-bit capture register) + 8-bit counter (with 8-bit capture register) mode 2 : 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) mode 3 : 16-bit counter (with a 16-bit capture register) ? timer 1 : 16-bit timer/counter that support pwm/ toggle output mode 0 : 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter (with toggle outputs ) mode 1 : 8-bit pwm with an 8-bit prescaler 2-channels mode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also present at the lower-order 8-bits) mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8-bits can be used as pwm.) ? timer 4 : 8-bit timer with a 6-bit prescaler ? timer 5 : 8-bit timer with a 6-bit prescaler ? timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs) ? timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs) ? base timer 1. the clock is selectable from sub-clock (32.768khz crystal oscillation), system clock or programmable prescaler output of timer 0. 2. interrupt are programmablein 5 different time schemes. ? high speed clock counter 1. can count clocks with a maximum clock rate of 20mhz (at a main clock of 10mhz). 2. can generate output real time.
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-3/25 ? serial interface ? sio 0 : 8-bit synchronous serial interface 1. lsb first/msb first-function available 2. an internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tcyc) 3. consecutive automatic data communication (1 to 256-bits) ? sio 1 : 8-bit asynchronous/s ynchronous serial interface mode 0 : synchronous 8-bit serial i o (2-wire or 3-wire, transmit clock 2 to 512 tcyc) mode 1 : asynchronous serial i o (half duplex, 8 data bits, 1 stop bit, baud-rate 8 to 2048 tcyc) mode 2 : bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tcyc) mode 3 : bus mode 2 (start detection, 8 data bits, stop detection) ? sio2 : 8-bit synchronous serial interface 1. lsb-first 2. internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tcyc) 3. consecutive automatic data communication (1 to 32 bytes) ? uart :2-channels 1. full duplex 2. 7/8/9 bit data bits selectable 3. 1stop bit 4. built-in baudrate generator ? ad converter ? 12-channel 8-bit ad converter ? pwm ? 4-channel synchronous variable 12-bit pwm ? remote receiver circuit (share with p73/int3/t0in terminal) ? noise rejection function (the filtering time of the noise rejection filter (1tcyc/32 tcyc/128 tcyc) can be switched by program.) ? watchdog ttimer ? external rc circuit is required. ? interrupt or system reset is activated when the timer overflows. ? interrupts ? 27-source and 10-vectored interrupt function : 1. three interrupt priorities, low (l), high (h) and high est (x) are supported with multi-level nesting possible. during interrupt handling, an equal or lower level interrupt request is refused. 2. if interrupt requests for two or more vector addresses occur at once, the higher level interrupt takes precedence. in the case of equal priority levels, th e vector with the lowest address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0/uart1, 2 receive 8 0003bh h or l sio1/sio2/uart1, 2 transmit 9 00043h h or l adc/t6/t7/pwm4, pwm5 10 0004bh h or l port 0/t4/t5/pwm0, pwm1 ? priority level : x > h > l ? for equal priority levels, vector with lowest address takes precedence.
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-4/25 ? subroutine stack levels ? a maximum of 3072 levels (set stack inside ram) ? multiplication and division ? 16-bits 8-bits (5 instruction-cycle times) ? 24-bits 16-bits (12 instruction-cycle times) ? 16-bits 8-bits (8 instruction-cycle times) ? 24-bits 16-bits (12 instruction-cycle times) ? oscillation circuits ? built-in rc oscillation circuit used for the system clock ? cf oscillation circuit used for the system clock ? crystal oscillation circuit used for the system clock ? system clock divider ? operable on the lowest power consumption ? minimum instruction cycle time (300ns, 600ns, 1.2 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, 76.8 s can be switched by program (when using 10mhz main clock) ? standby function ? halt mode the halt mode stops program execution while the peripheral circuits keep operating and minimizes power consumption. this operation mode can be released by a system reset or an interrupt request. ? hold mode the hold mode stops program execution and all osc illation circuits : cf, rc and crystal oscillations. this mode can be released by the following conditions. 1. supply "l" level to the reset terminal (res ) 2. supply the selected level to at l ease one of int0, int1, int2, int4, int5. 3. supply an interrupt condition to port 0. ? x?tal hold mode the x?tal hold mode stops program execution and all periph eral circuits except for the base timer. the crystal oscillator maintains its state at hold mode inception. this mode can be released by the following conditions. 1. supply "l" level to the reset terminal (res ). 2. supply the selected level to at least one of int0, int1, int2, int4, int5. 3. supply an interrupt condition to port 0. 4. supply an interrupt condition to the base timer circuit. ? shipping form ? qfp100e (lead free product) ? tqfp100 (lead free product) ? development tools ? evaluation (eva) chip : lc87ev690 ? emulator : eva62s + ecb876600d + sub875200 + pod100qfp or pod100sqfp type b : ice-b877300 + sub875200 + pod100qfp or pod100sqfp type b
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-5/25 package dimensions unit : mm 3151a package dimensions unit : mm 3274
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-6/25 pin assignment lc875bp4a/ lc875bm2a/ lc875bj0a/ LC875BH4A qip100e 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 pb7 p36 p35/urx2 p34/utx2 p33/urx1 p32/utx1 p31/pwm5 p30/pwm4 p27/int5/t1in p26/int5/t1in p25/int5/t1in p24/int4/t1in p23/int4/t1in p22/int4/t1in p21/int4/t1in p20/int4/t1in p07/t7o p06/t6o p05/cko p04 p03 p02 p01 p00 v ss 2 v dd 2 pwm0 pwm1 si2p3/sck20 si2p2/sck2 pb6 pb5 pb4 pb3 pb2 pb1 pb0 v ss 3 v dd 3 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pa0 pa1 pa2 pa3 pa4 pa5 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in p73/int3/t0in res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz si2p1/si2/sb2 si2p0/so2 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 v dd 4 v ss 4 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 10 11 12 13 14 1 5 16 17 1 8 19 20 21 22 23 24 25 26 27 28 29 3 0 top view
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-7/25 1 2 3 4 5 6 7 8 9 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in p73/int3/t0in res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pwm1 si2p3/sck20 si2p2/sck2 si2p1/si2/sb2 si2p0/so2 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 v dd 4 v ss 4 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 p17/t1pwmh/buz p16/t1pwml 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 p36 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 v ss 3 v dd 3 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pa0 pa1 pa2 pa3 pa4 pa5 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 lc875bp4a/ lc875bm2a/ lc875bj0a/ LC875BH4A tqfp100 p35/urx2 p34/utx2 p33/urx1 p32/utx1 p31/pwm5 p30/pwm4 p27/int5/t1in p26/int5/t1in p25/int5/t1in p24/int5/t1in p23/int4/t1in p22/int4/t1in p21/int4/t1in p20/int4/t1in p07/t7o p06/t6o p05/cko p04 p03 p02 p01 p00 v ss 2 v dd 2 pwm0 10 11 12 13 14 1 5 16 17 1 8 19 20 21 22 23 24 2 5 top view
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-8/25 pad coordinate values qip name tqfp qip name tqfp 1 pa3 98 51 si2p2/sck2 48 2 pa4 99 52 si2p3/sck20 49 3 pa5 100 53 pwm1 50 4 p70/int0/t0lcp/an8 1 54 pwm0 51 5 p71/int1/t0hcp/an9 2 55 v dd 2 52 6 p72/int2/t0in 3 56 v ss 2 53 7 p73/int3/t0in 4 57 p00 54 8 res 5 58 p01 55 9 xt1/an10 6 59 p02 56 10 xt2/an11 7 60 p03 57 11 v ss 1 8 61 p04 58 12 cf1 9 62 p05/cko 59 13 cf2 10 63 p06/t6o 60 14 v dd 1 11 64 p07/t7o 61 15 p80/an0 12 65 p20/int4/t1in 62 16 p81/an1 13 66 p21/int4/t1in 63 17 p82/an2 14 67 p22/int4/t1in 64 18 p83/an3 15 68 p23/int4/t1in 65 19 p84/an4 16 69 p24/int5/t1in 66 20 p85/an5 17 70 p25/int5/t1in 67 21 p86/an6 18 71 p26/int5/t1in 68 22 p87/an7 19 72 p27/int5/t1in 69 23 p10/so0 20 73 p30/pwm4 70 24 p11/si0/sb0 21 74 p31/pwm5 71 25 p12/sck0 22 75 p32/utx1 72 26 p13/so1 23 76 p33/urx1 73 27 p14/si1/sb1 24 77 p34/utx2 74 28 p15/sck1 25 78 p35/urx2 75 29 p16/t1pwml 26 79 p36 76 30 p17/t1pwmh/buz 27 80 pb7 77 31 pe0 28 81 pb6 78 32 pe1 29 82 pb5 79 33 pe2 30 83 pb4 80 34 pe3 31 84 pb3 81 35 pe4 32 85 pb2 82 36 pe5 33 86 pb1 83 37 pe6 34 87 pb0 84 38 pe7 35 88 v ss 3 85 39 v ss 4 36 89 v dd 3 86 40 v dd 4 37 90 pc7 87 41 pf0 38 91 pc6 88 42 pf1 39 92 pc5 89 43 pf2 40 93 pc4 90 44 pf3 41 94 pc3 91 45 pf4 42 95 pc2 92 46 pf5 43 96 pc1 93 47 pf6 44 97 pc0 94 48 pf7 45 98 pa0 95 49 si2p0/so2 46 99 pa1 96 50 si2p1/si2/sb2 47 100 pa2 97
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-9/25 system block diagram interrupt control cf standby control rc xtal clock generator ir pla rom pc sio0 sio1 timer 0 timer 1 bus interface port 1 port 0 port 7 port 8 adc port 2 int4, 5 acc b re g iste r c registe r psw rar ram stack pointe r watch dog time r pwm0 pwm1 base time r alu int0 - 3 noise rejection filter sio2 timer 4 timer 5 port 3 timer 6 timer 7 port e port c mrc port a port b port f pwm4 uart1 uart2 pwm5
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-10/25 pin description name i/o function description option v ss 1, v ss 2 v ss 3, v ss 4 - power supply pin (-) no v dd 1, v dd 2 v dd 3, v dd 4 - power supply pin (+) no port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 4-bit units ? pull-up resistor can be turned on and off in 4-bit units ? hold release input ? port 0 interrupt input ? pin functions p05 : system clock output p06 : timer 6 toggle output p07 : timer 7 toggle output yes port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? pin functions p10: sio0 data output p11 : sio0 data input, bus i/o p12 : sio0 clock i/o p13 : sio1 data output p14 : sio1 data input, bus i/o p15 : sio1 clock i/o p16 : timer 1 pwml output p17 : timer 1 pwmh output/buzzer output yes port 2 ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? other functions p20 to p23 : int4 input/hold release inpu t/timer 1 event input/timer 0l capture input/timer 0h capture input p24 to p27 : nt5 input/hold release inpu t/timer 1 event input/timer 0l capture input/timer 0h capture input ? interrupt detection style rising falling rising/ falling h level l level int4 enable enable enable disable disable int5 enable enable enable disable disable p20 to p27 i/o yes port 3 p30 to p36 i/o ? 7-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? pin functions p30 : pwm4 output p31 : pwm5 output p32 : uart1 transmit p33 : uart1 receive p34 : uart2 transmit p35 : uart2 receive yes continued on next page.
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-11/25 continued from preceding page. name i/o function description option port 7 ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? other functions p70 : int0 input/hold release input/timer 0l capture input/output for watchdog timer p71 : int1 input/hold release input/timer 0h capture input p72 : int2 input/hold release input/timer 0 event input/timer 0l capture input p73 : int3 input with noise filter/timer 0 event input/timer 0h capture input ? interrupt acknowledge type rising falling rising/ falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable p70 to p73 i/o ? ad converter input port : an8 (p70), an9 (p71) no port 8 p80 to p87 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? other functions p80 to p87 : ad converter input port no port a pa0 to pa5 i/o ? 6-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units yes port b pb0 to pb7 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units yes port c pc0 to pc7 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units yes port e pe0 to pe7 i/o ? 8-bit i/o port ? i/o specifiable in 2-bit units ? pull-up resistor can be turned on and off in 1-bit units no port f pf0 to pf7 i/o ? 8-bit i/o port ? i/o specifiable in 2-bit units ? pull-up resistor can be turned on and off in 1-bit units no sio2 port si2p0 to si2p3 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? other functions si2p0 : sio2 data output si2p1 : sio2 data input, bus input/output si2p2 : sio2 clock input/output si2p3 : sio2 clock output no pwm0 o ? pwm0 output port ? general-purpose i/o available no pwm1 o ? pwm1 output port ? general-purpose i/o available no res i reset pin no xt1 i ? input terminal for 32.768khz x'tal oscillation ? other function an10 : ad converter input port general input port when not in use, connect terminal to v dd 1. no xt2 i/o ? output terminal for 32.768khz x'tal oscillation ? other function an11 : ad converter input port general input port when not in use, set as oscillation and leave terminal open no cf1 i input terminal for ceramic resonator no cf2 o output terminal for ceramic resonator no
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-12/25 port output configuration output configuration and pull-up resistor options are shown in the following table. input is possible even when a port is in output mode. terminal option applies to : option output format pull-up resistor 1 cmos programmable (note 1) p00 to p07 1 bit 2 nch-open drain none 1 cmos programmable p10 to p17 p20 to p27 p30 to p36 1 bit 2 nch-open drain programmable 1 cmos programmable pa0 to pa5 pb0 to pb7 pc0 to pc7 1 bit 2 nch-open drain programmable pe0 to pe7 pf0 to pf7 - none cmos programmable p70 - none nch-open drain programmable p71 to p73 - none cmos programmable p80 to p87 - none nch-open drain none si2p0, si2p2 si2p3 pwm0, pwm1 - none cmos none si2p1 - none cmos (when used as general port) nch-open drain (when used for sio2 data) none xt1 - none input only none xt2 - none output for 32.768khz crystal oscillation nch-open drain (when in general-purpose output mode) none note 1 programmable pull-up resistor of port 0 is specified in nibble units (p00 to p03, p04 to p07). note : to reduce v dd signal noise and to increase the dura tion of the backup battery supply, v ss 1, v ss 2, v ss 3 and v ss 4 should connect to each other and they should also be grounded. example 1 : during backup in hold mode, port output ?h? level is supplied from the back-up capacitor. v ss 1 v ss 2 v ss 3 v dd 3 v dd 2 v dd 1 lsi v dd 4 v ss 4 power supply back-up capacitor
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-13/25 example 2 : during backup in hold mode, output is not held high and its value in unsettled. power supply back-up capacitor v ss 1 v ss 2 v ss 3 v dd 3 v dd 2 v dd 1 lsi v dd 4 v ss 4
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-14/25 absolute maximum ratings / ta = 25c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit supply voltage v dd max v dd 1, v dd 2, v dd 3, v dd 4 v dd 1=v dd 2 =v dd 3=v dd 4 -0.3 +6.5 input voltage v i (1) xt1, xt2, cf1 -0.3 v dd +0.3 output voltage v o (1) pwm0, pwm1 -0.3 v dd +0.3 input/output voltage vio (1) ? ports 0, 1, 2 ? ports 3, 7, 8 ? ports a, b, c, e, f ? si2p00 to si2p03 ? pwm0, pwm1 -0.3 v dd +0.3 v ioph (1) ? ports 0, 1, 2, 3 ? ports a, b, c, e, f ? si2p00 to si2p03 ? pwm0, pwm1 ? cmos output ? for each pin. -10 peak output current ioph (2) p71 to p73 for each pin. -5 ioah (1) p71 to p73 total of all pins -5 ioah (2) ? port 1 ? pwm0, pwm1 ? port 3 ? si2p00 to si2p03 total of all pins -30 ioah (3) ports 0, 2 total of all pins -20 ioah (4) port b total of all pins -20 high level output current total output current ioah (5) ports a, c total of all pins -20 iopl (1) ? p02 to p07 ? ports 1, 2, 3 ? ports a, b, c, e, f ? si2p00 to si2p03 ? pwm0, pwm1 for each pin. 20 iopl (2) p00, p01 for each pin. 30 peak output current iopl (3) ports 7, 8 for each pin. 5 ioal (1) port 7 total of all pins 15 ioal (2) port 8 total of all pins 15 ioal (3) ? pwm0, pwm1 ? port 3 ? si2p00 to si2p03 total of all pins 40 ioal (4) ports 0, 2, 3 total of all pins 80 ioal (5) port b total of all pins 40 ioal (6) ports a, c total of all pins 40 ioal (7) port f total of all pins 40 low level output current total output current ioal (8) port 1, e total of all pins 70 ma qip100e 519 maximum power consumption pd max tqfp100 ta= -30 to +70c 363 mw operating temperature range topr -30 70 storage temperature range tstg -55 125 c
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-15/25 recommended operating range / ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit 0.294 s tcyc 200 s 4.5 5.5 operating supply voltage range v dd (1) v dd 1=v dd 2 =v dd 3=v dd 4 0.588 s tcyc 200 s 2.5 5.5 hold voltage vhd v dd 1=v dd 2 =v dd 3=v dd 4 ram and register data are kept in hold mode. 2.0 5.5 v ih (1) ? ports 1, 2, 3 ? si2p00 to 03 ? p71 to p73 ? p70 port input /interrupt 2.5 to 5.5 0.3v dd +0.7 v dd v ih (2) ? ports 0, 8 ? ports a, b, c, e, f 2.5 to 5.5 0.3v dd +0.7 v dd v ih (3) port 70 watchdog timer 2.5 to 5.5 0.9v dd v dd input high voltage v ih (4) xt1, xt2, cf1, res 2.5 to 5.5 0.75v dd v dd v il (1) ? ports 1, 2, 3 ? si2p00 to 03 ? p71 to p73 ? p70 port input /interrupt 2.5 to 5.5 v ss 0.1v dd +0.4 v il (2) ? ports 0, 8 ? ports a, b, c, e, f 2.5 to 5.5 v ss 0.15v dd +0.4 v il (5) port 70 watchdog timer 2.5 to 5.5 v ss 0.8v dd -1.0 input low voltage v il (6) xt1, xt2, cf1, res 2.5 to 5.5 v ss 0.25v dd v 4.5 to 5.5 0.294 200 operation cycle time tcyc 2.5 to 5.5 0.588 200 s ? leave cf2 pin open ? system clock divider set to 1/1 ? external clock duty=505% 4.5 to 5.5 0.1 10 ? leave cf2 pin open ? system clock divider set to 1/1 ? external clock duty=505% 2.5 to 5.5 0.1 5 ? leave cf2 pin open ? system clock divider set to 1/2 4.5 to 5.5 0.2 20.4 external system clock frequency fexcf (1) cf1 ? leave cf2 pin open ? system clock divider set to 1/2 2.5 to 5.5 0.1 10 fmcf (1) cf1, cf2 10mhz ceramic resonator oscillation refer to figure 1 4.5 to 5.5 10 fmcf (2) cf1, cf2 5mhz ceramic resonator oscillation refer to figure 1 2.5 to 5.5 5 fmrc rc oscillation 2.5 to 5.5 0.3 1.0 2.0 fmmrc frequency variable rc oscillation source oscillation 2.5 to 5.5 50 mhz oscillation frequency range (note1) fsx?tal xt1, xt2 32.768khz crystal resonator oscillation refer to figure 2 2.5 to 5.5 32.768 khz note 1 : the oscillation parameters are shown on tables 1 and 2.
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-16/25 electrical characteristics / ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit i ih (1) ? ports 0, 1, 2 ? ports 3, 7, 8 ? ports a, b, c ? si2p00 to si2p03 ? res ? pwm0, pwm1 ? output disable ? pull-up resistor off ? v in =v dd (including the off-leak current of the output tr.) 2.5 to 5.5 1 i ih (2) xt1, xt2 ? using as an input port ? v in =v dd 2.5 to 5.5 1 input high current i ih (3) cf1 v in =v dd 2.5 to 5.5 15 i il (1) ? ports 0, 1, 2 ? ports 3, 7, 8 ? ports a, b, c, e, f ? si2p00 to si2p03 ? res ? pwm0, pwm1 ? output disable ? pull-up resistor off ? v in =v ss (including the off-leak current of the output tr.) 2.5 to 5.5 -1 i il (2) xt1, xt2 ? using as an input port ? v in =v ss 2.5 to 5.5 -1 input low current i il (3) cf1 v in =v ss 2.5 to 5.5 -15 a v oh (1) i oh = -1.0ma 4.5 to 5.5 v dd -1 v oh (2) ? ports 0, 1, 2, 3 ? ports a, b, c, e, f ? si2p00 to si2p03 i oh = -0.1ma 2.5 to 5.5 v dd -0.5 v oh (3) port 71, 72, 73 i oh = -1.5ma 4.5 to 5.5 v dd -1 v oh (4) i oh = -6.0ma 4.5 to 5.5 v dd -1 v oh (5) i oh = -1.6ma 4.5 to 5.5 v dd -0.4 output high voltage v oh (6) pwm0, pwm1 p30, p31 (pwm4, 5 output mode) i oh = -1.0ma 2.5 to 5.5 v dd -0.4 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.6ma 4.5 to 5.5 0.4 v ol (3) ? ports 0, 1, 2, 3 ? ports a, b, c, e, f ? si2p00 to si2p03 ? pwm0, pwm1 i ol =1.0ma 2.5 to 5.5 0.4 v ol (4) p00, p01 i ol =30ma 4.5 to 5.5 1.5 output low voltage v ol (5) ports 7, 8 i ol =1.0ma 2.5 to 5.5 0.4 v pull-up resistor rpu ? ports 0, 1, 2, 3 ? port 7 ? ports a, b, c, e, f v oh =0.9v dd 2.5 to 5.5 15 40 70 k ? hysteresis voltage vhis ? res ? port 1 ? port 2 ? port 3 ? port 7 ? sip00 to sip03 2.5 to 5.5 0.1v dd v pin capacitance cp all pins ? all pins except the measured terminal : v in =v ss ? f=1mhz ? ta=25c 2.5 to 5.5 10 pf
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-17/25 serial input/output characteristics / ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit cycle tsck (1) 2 tsckl (1) 1 low level pulse width tsckla (1) 1 tsckh (1) 1 high level pulse width tsckha (1) sck0 (p12), si2p2 refer to figure 6 2.5 to 5.5 4(sio0) 5(sio2) cycle tsck (2) 2 low level pulse width tsckl (2) 1 input clock high level pulse width tsckh (2) sck1 (p15) refer to figure 6 2.5 to 5.5 1 cycle tsck (3) 4/3 tcyc tsckl (3) ? cmos output ? refer to figure 6 1/2 sck0 (p12) sio0 3/4 low level pulse width tsckla (2) si2p2, si2p3 sio2 1 tsckh (3) 1/2 sck0 (p12) sio0 2 high level pulse width tsckha (2) sck0 (p12), si2p2 si2p3 si2p2, si2p3 sio2 2.5 to 5.5 7/4 tsck cycle tsck (4) 2 tcyc low level pulse width tsckl (4) 1/2 serial clock output clock high level pulse width tsckh (4) sck1 (p15) ? cmos output ? refer to figure 6 2.5 to 5.5 1/2 tsck data set-up time tsdi 0.03 serial input data hold time thdi sb0 (p11), sb1 (p14), si2p1 si0 si1 ? data set-up to si0clk ? data hold from si0clk ? refer to figure 6 2.5 to 5.5 0.03 serial output output delay time tdd0 so0 (p10), so1 (p13), sb0 (o11), sb1 (p14), si2p0, si2p1 ? data hold from si0clk ? time delay from si0clk trailing edge to the so data change in the open drain ? refer to figure 6 2.5 to 5.5 1/3tcyc +0.05 s
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-18/25 pulse input conditions / ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit tpih (1) tpil (1) int0 (p70), int1 (p71), int2 (p72) int4 (p20 to p23) int5 (p24 to p27) ? interrupt acceptable ? timer 0 and 1 event input acceptable 2.5 to 5.5 1 tpih (2) tpil (2) int3 (p73) (the noise rejection clock is selected to 1/1.) ? interrupt acceptable ? timer 0 event input acceptable 2.5 to 5.5 2 tpih (3) tpil (3) int3 (p73) (the noise rejection clock is selected to 1/32.) ? interrupt acceptable ? timer 0 event input acceptable 2.5 to 5.5 64 tpih (4) tpil (4) int3 (p73) (the noise rejection clock is selected to 1/128.) ? interrupt acceptable ? timer 0 event input acceptable 2.5 to 5.5 256 tcyc high/low level pulse width tpil (5) res reset acceptable 2.5 to 5.5 200 s ad converter characteristics / ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute precision et (note 2) 3.0 to 5.5 1.5 lsb 4.5 to 5.5 15.10 (tcyc= 0.588 s) 97.92 (tcyc= 3.06 s) ad conversion time=32 tcyc (adcr2=0) (note 3) 3.0 to 5.5 31.36 (tcyc= 0.980 s) 97.92 (tcyc= 3.06 s) 4.5 to 5.5 18.82 (tcyc= 0.294 s) 97.92 (tcyc= 1.53 s) conversion time tcad ad conversion time=64 tcyc (adcr2=1) (note 3) 3.0 to 5.5 62.72 (tcyc= 0.980 s) 97.92 (tcyc= 1.53 s) s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0 (p80) to an7 (p87) an8 (p70) an9 (p71) an10 (xt1) an11 (xt2) vain=v ss 3.0 to 5.5 -1 a note 2 : absolute precision exclud es the quantizing error (1/2 lsb). note 3 : the conversion time is the time from executing the ad conversion instruction to setting the complete digital conversion value in the register.
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-19/25 current dissipation characteristics / ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit iddop (1) ? fmcf=10mhz by ceramic resonator ? fmx?tal=32.768khz by crystal oscillation ? system clock : cf oscillation (10mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/1 divided 4.5 to 5.5 10 15 iddop (2) ? cf1=20mhz by external clock ? fmx?tal=32.768khz by crystal oscillation ? system clock : cf1 oscillation (20mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/2 divided 2.5 to 5.5 10.5 16 iddop (3) 4.5 to 5.5 5.5 8 iddop (4) ? fmcf=5mhz by ceramic resonator ? fmx'tal=32.768khz by crystal oscillation ? system clock : cf oscillation (5mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/1 divided 2.5 to 4.5 3 6 iddop (5) 4.5 to 5.5 0.7 4 iddop (6) ? fmcf=0hz (when oscillation stops) ? fmx'tal=32.768khz by crystal oscillation ? system clock : rc oscillation ? frequency variable rc oscillation stops ? 1/2 divided 2.5 to 4.5 0.3 1.5 iddop (7) 4.5 to 5.5 2 6 iddop (8) ? fmcf=0hz (when oscillation stops) ? fmx'al=32.768khz by crystal oscillation ? system clock : 1mhz with frequency variable rc oscilatin ? internal rc oscillation stops ? 1/2 divided 2.5 to 5.5 0.7 3.5 ma iddop (9) 4.5 to 5.5 27 60 current drain during basic operation (note 4) iddop (10) v dd 1 =v dd 2 =v dd 3 =v dd 4 ? fmcf=0hz (when oscillation stops) ? fmx'al=32.768khz by crystal oscillation ? system clock : x'tal oscillation (32.768khz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/2 divided 2.5 to 4.5 12 40 a note 4 : the current of the output transist ors and pull-up mos tran sistors are excluded. continued on next page.
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-20/25 continued from preceding page. limits parameter symbol pins conditions v dd [v] min typ max unit iddhalt (1) ? halt mode ? fmcf=10mhz by ceramic resonator ? fmx?tal=32.768khz by crystal oscillation ? system clock : cf oscillation (10mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/1 divided 4.5 to 5.5 2.5 5 iddhalt (2) ? halt mode ? cf1=20mhz by external clock ? fmx?tal=32.768khz by crystal oscillation ? system clock : cf1 oscillation (20mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/2 divided 4.5 to 5.5 3.2 6 iddhalt (3) 4.5 to 6.0 1.5 3 iddhalt (4) ? halt mode ? fmcf=5mhz by ceramic resonator ? fmx?tal=32.768khz by crystal oscillation ? system clock : cf oscillation (5mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/1 divided 2.5 to 4.5 0.7 1.5 iddhalt (5) 4.5 to 5.5 0.3 1 iddhalt (6) ? halt mode ? fmcf=0hz (when oscillation stops) ? fmx?tal=32.768khz by crystal oscillation ? system clock : rc oscillation ? frequency variable rc oscillation stops ? 1/2 divided 2.5 to 4.5 0.15 0.5 iddhalt (7) 4.5 to 5.5 1.6 2.5 iddhalt (8) ? halt mode ? fmcf=0hz (when oscillation stops) ? fmx'tal=32.768khz by crystal oscillation ? system clock : 1mhz with frequency variable rc oscilatin ? internal rc oscillation stops ? 1/2 divided 2.5 to 4.5 0.6 1.8 ma iddhalt (9) 4.5 to 5.5 16 40 current drain in halt mode (note 4) iddhalt (10) v dd 1 =v dd 2 =v dd 3 =v dd 4 ? halt mode ? fmcf=0hz (when oscillation stops) ? fmx'tal=32.768khz by crystal oscillation ? system clock : x'tal oscillation (32.768khz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/2 divided 2.5 to 4.5 5 25 iddhold (1) 4.5 to 5.5 0.015 10 current drain during hold mode iddhold (2) v dd 1 ? hold mode ? cf1=v dd or leave it open (when using external clock) 2.5 to 4.5 0.001 5 iddhold (3) 4.5 to 5.5 14 35 current drain during time-base clock hold mode iddhold (4) v dd 1 ? time-base clock hold mode ? cf1=v dd or leave it open (when using external clock) ? fmx'tal=32.768khz by crystal oscillation 2.5 to 4.5 3.8 20 a note 4 : the current of the output transist ors and pull-up mos tran sistors are excluded.
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-21/25 uart (full duplex) operating conditions / ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit clock rate ubr, ubr2 utx1 (p32), rtx1 (p33), utx2 (p33), rtx2 (p34) 2.5 to 5.5 16/3 8192/3 tcyc data length : 7, 8 and 9 bits (lsb first) stop bits : 1-bit parity bits : non continuous 8-bit data transmit mode (first transmit data = 55h) continuous 8-bit data receive mode (first transmit data = 55h) stop bit received data (lsb first) ubr, ubr2 beginning of reception start bit end of reception start bit stop bit transmit data (lsb first) beginning of transmission end of transmittion ubr, ubr2
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-22/25 main system clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions : 1. using the standard oscillation evaluation board sanyo has provided. 2. using the external peripheral parts with the indicated value. 3. the recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. table 1. recommended circuit parameters for the main system clock using the ceramic resonator recommended circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 c2 rd1 operating supply voltage range typ max note csls10m0g53-r0 (10pf) (10pf) 150 ? 4.5 to 5.5v internal c1,c2 10mhz murata cstls10m0g52-b0 (10pf) (10pf) 100 ? 4.5 to 5.5v internal c1,c2 cstls5m00g53-r0 (15pf) (15pf) 470 ? 2.5 to 5.5v internal c1,c2 5mhz murata cstls5m00g53-b0 (15pf) (15pf) 470 ? 2.5 to 5.5v internal c1,c2 *the oscillation stabilizing time is a period until the oscillation becomes stable after v dd becomes higher than minimum operating voltage. (refer to figure 4) subsystem clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions : 1. using the standard oscillation evaluation board sanyo has provided. 2. using the external peripheral parts with the indicated value. 3. the recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. table 2. recommended circuit parameters for the subsystem clock using the crystal oscillation recommended circuit parameters oscillation stabilizing time frequency manufacturer oscillator c3 c4 rf rd2 operating supply voltage range typ max note 32.768khz seiko epson mc-306 15pf 15pf open 390k ? 2.5 to 5.5v *the oscillation stabilizing time is the period until the oscillation becomes stable, after executing the instruction which starts the sub-clock oscillator or after releasing a hold mode. (refer to figure 4) notes : since the oscillation frequency precision is affected by the circuit pattern, place the oscillation related parts as close to the oscillation pins as possible, using the shortest possible pattern length. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit figure 3 ac timing point c3 rd2 c4 x?tal xt2 xt1 rf c1 c2 cf cf2 cf1 rd1 0.5v dd
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-23/25 reset time and oscillation stabilizing time hold release signal and oscillation stabilizing time figure 4 oscillation stabilizing time v dd limit power suppl y res internal rc oscillation cf1, cf2 xt1, xt2 operation mode reset time tmscf tmsxtal unfixed reset instruction execution v dd gnd internal rc oscillation cf1, cf2 xt1, xt2 operation mode hold release signal hold release signal valid tmscf tmsxtal hold halt
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-24/25 figure 5 reset circuit figure 6 serial input/output test condition figure 7 pulse input timing condition c res v dd r res res (note) select c res and r res value to assure that at least 200 s reset time is generated after the v dd becomes higher than the minimum operating voltage. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 si0clk : datain : dataout : dataout : datain : si0clk : dataout : datain : si0clk : tsck tsckl tsckh thdi tsdi tddo tsckla tsckha thdi tsdi tddo data ram transmission period (only sio0, 2) data ram transmission period (only sio0, 2)
lc875bp4a/875bm2a/875bj0a/875bh4a no.7972-25/25 ps specifications of any and all sanyo semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides information as of august, 2005. specifications and information herein are subject to change without notice.

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